The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low R×C (resistance×capacitance) interconnect pattern with electromigration resistance, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization. High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the R×C delay caused by the interconnect wiring increases.
As device features plunge into the deep submicron regime, interconnect technology is transitioning from aluminum-based to copper-based metallurgy. This technological evolution has come about through the adoption of damascene and dual-damascene process flows involving electrolytic copper-plating and chemical mechanical polishing (CMP) techniques. The technological benefits of Cu, such as reduced R×C delay are clear; however, various reliability issues have evolved. For example, due to Cu diffusion through interlayer dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology employing a diffusion barrier layer (capping layer). For example, conventional practices comprise forming a damascene opening in an interlayer dielectric, depositing a barrier layer, such as TaN, lining the opening and on the surface of the interlayer dielectric, filling the opening with Cu or a Cu alloy layer, CMP, and forming a silicon nitride capping layer on the exposed surface of the Cu or Cu alloy. It was found, however, that capping layers, such as silicon nitride, deposited by plasma enhanced chemical vapor deposition (PECVD), exhibit poor adhesion to the Cu or Cu alloy surface. Consequently, the capping layer is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing electromigration and stress migration resistance.
It has been proposed to employ a tantalum (Ta) layer to cap inlaid Cu metallization. Such a process flow is schematically illustrated in FIGS. 1A through 1G. Adverting to FIG. 1A, a dielectric layer 11 is formed over a substrate 10. An opening 12 is then formed in dielectric layer 11 as illustrated in FIG. 1B. Subsequently, a diffusion barrier layer 13, such as Ta or tantalum nitride is then deposited to line the opening and Cu or a Cu alloy 14 deposited filling the opening and forming an overburden as illustrated in FIG. 1C. CMP is then implemented forming inlaid Cu having an upper surface substantially coplanar with the upper surface of dielectric layer 11 as illustrated in FIG. 1D.
Adverting to FIG. 1E, a recess 16 is formed in Cu layer 15. An impetus to employing Ta as a capping layer for inlaid Cu is an improvement in electromigration and stress migration performance. It was experimentally determined that the amount of Ta on top of copper to yield the electromigration benefit is only 40 Å. However, to reliably ensure that this minimum thickness of Ta is present on all Cu lines subsequent to CMP, it is necessary to etch a recess (16 in FIG. 1E) into the Cu to approximately 400 Å and subsequently deposit about the same thickness of Ta. Because of dishing effects for wide Cu lines, Ta will be thinned more on the wide lines resulting in nearly full thickness of Ta on the narrow lines and less than 100 Å on the wide lines, thereby meeting the minimum thickness requirement of 40 Å.
Adverting to FIG. 1F, a layer of Ta 17 is deposited filling the recess and forming an overburden. Subsequently, CMP is implemented forming Ta capping layer 18 having an upper surface substantially coplanar with the upper surface of dielectric layer 11 as illustrated in FIG. 1G. Subsequent processing may be implemented in a conventional manner, as by depositing overlying dielectric layers and forming vias in electrical contract to the Ta copper lines.
A disadvantage of the Ta capping layer approach is an increase in via resistance which would detract from the benefit of the Ta capping layer compared to not having a capping layer. If the Ta capping layer is etched away over the inlaid Cu in the area of the via during the subsequent via etch processing steps, several problems evolve, such as additional processing and attendant increased manufacturing costs, via corner bevelling and Cu contamination.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices having reliably capped Cu interconnect Cu features with reduced via resistance and improved electromigration and stressed migration performance.